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LTC1264 High Speed, Quad Universal Filter Building Block
FEATURES
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DESCRIPTIO
High Speed, Up to 250kHz Center Frequency Four Identical Filters in a 0.3" Wide Package Clock-to-Center Frequency Ratio of 20:1 Double-Sampling, Improved Aliasing Operates from 2.37V to 8V Power Supplies Customized Version with Internal Resistors Available Low Noise Low Harmonic Distortion
The LTC (R)1264 consists of four identical, high speed 2nd order switched-capacitor filter building blocks designed for center frequencies up to 250kHz. Each building block, together with three to five resistors, can provide 2nd order functions like lowpass, highpass, bandpass and notch. The center frequency of each 2nd order section is tuned via an external clock. The clock-to-center frequency ratio is internally set to 20:1, but it can be modified via external resistors. The aliasing performance of the LTC1264 is improved by double-sampling each 2nd order section. Input signal frequencies can reach up to twice the clock frequency before any alias products will be detectable. For Q 5 and for TA < 85C, the maximum center frequency is 160kHz. For Q 2, the maximum center frequency is 250kHz. Up to 8th order filters can be realized by cascading all four 2nd order sections. A customized monolithic version of the LTC1264 including internal thin film resistors can be obtained.
APPLICATI
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S
Digital Communications Spread Spectrum Communications Spectral Analysis Loran Receivers Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
50k IN 10k HPB/NB 50k BPB MAXIMUM POWER fCENTER SUPPLY 160kHz 7.5V 120kHz 5V 60kHz Single 5V 0.1F LPB SB AGND V+ SA LPA 50k BPA 10k HPA/NA INV A 50k INV B
Clock-Tunable 8th Order Bandpass Filter, fCENTER = fCLK /20
50k INV C 10k HPC/NC 50k BPC LPC LTC1264 SC V- CLK SD LPD BPD HPD/ND 10k INV D 50k
1264 TA01
Gain vs Frequency 100kHz Bandpass, f -3dB Bandwidth = fCENTER/10
10 0 -10 -20
GAIN (dB)
-30 -40 -50
fCLK
0.1F
OUT 50k
-60 -70 -80 10k 100k FREQUENCY (Hz) 1M
1264 TA02
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UO
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1
LTC1264 ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW INV B HPB/NB BPB LPB SB AGND V+ SA LPA 1 2 3 4 5 6 7 8 9 24 INV C 23 HPC/NC 22 BPC 21 LPC 20 SC 19 V - 18 CLK 17 SD 16 LPD 15 BPD 14 HPD/ND 13 INV D S PACKAGE 24-LEAD PLASTIC SOL
Total Supply Voltage (V + to V -) .............................. 16V Input Voltage (Note 2) ........... (V + + 0.3V) to (V - - 0.3V) Output Short-Circuit Duration .......................... Indefinite Power Dissipation............................................. 400mW Burn-In Voltage ...................................................... 16V Operating Temperature Range ............... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1264CN LTC1264CS
BPA 10 HPA/NA 11 INV A 12 N PACKAGE 24-LEAD PLASTIC DIP
TJMAX = 110C, JA = 65C/W (N) TJMAX = 110C, JA = 85C/W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
(Internal Op Amps) TA = 25C, unless otherwise noted.
PARAMETER Operating Supply Range Voltage Swings CONDITIONS VS = 2.375V, RL = 5k VS = 5V, RL = 5k
q
MIN 2.375 3.2 3.1
TYP 1.5 3.7 6 3 80 7 10
MAX 8
VS = 7.5, RL = 5k Output Short-Circuit Current (Source/Sink) DC Open-Loop Gain GBW Product Slew Rate
UNITS V V V V V mA dB MHz V/s
(Complete Filter) VS = 5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz, Q = 5, TA = 25C, unless otherwise noted.
PARAMETER Center Frequency Range, fO (Note 1) CONDITIONS VS = 7.5V, TA < 85C, Q < 2 VS = 5V, TA < 85C, Q < 2 VS = 2.5V, TA < 85C, Q < 2 VS = 7.5V
q
MIN
Clock-to-Center Frequency Ratio, fCLK /fO Center Frequency Error (Note 3)
TYP 0.1 - 250 0.1 - 200 0.1 - 100 20:1 0.1 0.2
MAX
UNITS kHz kHz kHz % % % % % % % % % ppm/C ppm/C
VS = 5V
q
0.7 0.8 0.8 1.0 0.8 1.0 7.0
Clock-to-Center Frequency Ratio, Side-to-Side Matching Q Accuracy fO Temperature Coefficient Q Temperature Coefficient
VS = 2.375V VS 5V
q
- 1.6 0.4 - 2.7
q
VS = 5V fCLK < 2MHz fCLK < 2MHz
1 5
2
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LTC1264
ELECTRICAL CHARACTERISTICS
(Complete Filter) VS = 5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz, Q = 5, TA = 25C, unless otherwise noted.
PARAMETER DC Offset Voltage (Note 2) CONDITIONS VOS1 (DC Offset of Input Inverter) VOS2 (DC Offset of First Integrator) VOS3 (DC Offset of Second Integrator) VS = 7.5V (fCLK is a Square Wave) VS = 5V (fCLK is a Square Wave) VS = 2.375V (fCLK is a Square Wave) VS = 7.5V, TA = 25C VS = 5V MIN
q q q
TYP
MAX 20 45 45
Clock Feedthrough
Maximum Clock Frequency Power Supply Current
9
q
160 120 90 6 14
23 26
UNITS mV mV mV VRMS VRMS VRMS MHz mA mA
The q denotes specifications which apply over the full operating temperature range. Note 1: Please refer to Typical Maximum Q vs Clock Frequency graphs. Note 2: Calculations of output DC offsets of one 2nd order section. Also see Block Diagram. MODE 1 1b 2 3 VOSN PINS 2, 11, 14, 23 VOS1[(1Q) + 1 ||HOLP ||] - VOS3 /Q VOS1[(1/Q) + 1 + R2/R1] - VOS3 /Q [VOS1(1 + R2/R1 + R2/R3 + R2/R4) - VOS3(R2/R3)] * [R4/(R2 + R4)] + VOS2[R2/(R2 + R4)] VOS2
Note 3: The center frequency fO, error is calculated as: fO(measured) - fO(ideal) * 100 fO (ideal)
VOSBP PINS 3, 10, 15, 22 VOS3 VOS3 VOS3 VOS3 VOSN - VOS2
VOSLP PINS 4, 9, 16, 21 (VOSN - VOS2)(1 + R5/R6) VOSN - VOS2 VOS1[1 + R4/R1 + R4/R2 + R4/R3] - VOS2(R4/R2) - VOS3(R4/R3)
TYPICAL PERFOR A CE CHARACTERISTICS
Typical Maximum Q vs Clock Frequency
26 24 22 20 18 16 14 12 10 8 6 4 2 0 A VS = 7.5V TA 85C 26 24 22 20 18 16 14 12 10 8 6 4 2 0
TYPICAL MAXIMUM Q
TYPICAL MAXIMUM Q
TYPICAL MAXIMUM Q
A. MODES 1, 1b B. MODES 3, 3a B
1.5
2.0
2.5 3.0 3.5 4.0 4.5 CLOCK FREQUENCY (MHz)
UW
5.0
1264 G01
Typical Maximum Q vs Clock Frequency
A
Typical Maximum Q vs Clock Frequency
20
VS = 5V TA 85C A. MODES 1, 1b B. MODES 3, 3a
A
18 16 14 12 10 8 6 4 2 B
VS = SINGLE 5V TA 85C A. MODES 1, 1b B. MODES 3, 3a
B
1.0
1.5
3.0 2.0 3.5 2.5 CLOCK FREQUENCY (MHz)
4.0
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0 1.0
1.2 1.6 1.8 1.4 CLOCK FREQUENCY (MHz)
2.0
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3
LTC1264
TYPICAL PERFOR A CE CHARACTERISTICS
Typical Bandpass Gain Error vs Clock Frequency
5
TYPICAL BANDPASS GAIN ERROR (dB) TYPICAL BANDPASS GAIN ERROR (dB)
4
4
TYPICAL BNADPASS GAIN ERROR (dB)
MODE 1 Q=2 TA = 25C
3 VS = 5V 2 VS = 7.5V
1
0 2.0
2.4 3.2 3.6 2.8 CLOCK FREQUENCY (MHz)
Typical Bandpass Gain Error vs Clock Frequency
5
TYPICAL BANDPASS GAIN ERROR (dB)
4
MODE 3 Q=4 TA = 25C VS = SINGLE 5V
fCLK /fO
3 VS = 7.5V 2
1
0
1
Noise vs R2/R4 Ratio
600 500 400 300 200 100 0
POWER SUPPLY CURRENT (mA)
NOISE (VRMS)
0
0.2
4
UW
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Typical Bandpass Gain Error vs Clock Frequency
5 MODE 1 Q=4 TA = 25C VS = 5V 3 5
Typical Bandpass Gain Error vs Clock Frequency
MODE 1 VS = SINGLE 5V TA = 25C
4
3 Q=4 2 Q=2 1
2 VS = 7.5V 1
4.0
0 2.0
2.4 3.2 3.6 2.8 CLOCK FREQUENCY (MHz)
4.0
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0 1.3
1.4
1.7 1.8 1.9 1,5 1.6 CLOCK FREQUENCY (MHz)
2.0
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Ratio (fCLK /fO) vs Clock Frequency
20.5 20.4 20.3 20.2 20.1 20.0 19.9 19.8 19.7 19.6 Q=2 Q = 10 Q=4 BANDPASS OUT MODE 1 VS = 7.5V
VS = 5V
2
3
4
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19.5
1
2
3
4
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CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
Power Supply Current vs Supply Voltage
48
MODE 3 VS = 7.5V Q=2 R2 f fO = CLK 20 R4
44 40 36 32 28 24 20 16 12 8 4 0 -55C 25C 125C
0.4 0.6 0.8 RESISTOR RATIO (R2/R4)
1.0
1264 G12
02
4 6 8 10 12 14 16 18 20 22 24 POWER SUPPLY VOLTAGE (V+ - V -)
1264 G14
LTC1264
PI FU CTIO S
V +, V - (Pins 7, 19): Power Supply Pins. The V + (Pin 7) and the V - (Pin 19) should each be bypassed with a 0.1F capacitor to an adequate analog ground. The filter's power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than 1V/s. When V + is applied before V - and V - is allowed to go above ground, a diode should clamp V - to prevent latch-up. Figures 1 and 2 show typical connections for dual and single supply operation. AGND (Pin 6): Analog Ground Pin. The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, Pin 6 should be connected to the analog ground plane. For single supply operation, Pin 6 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1F capacitor (Figure 2). For single 5V operation and fCLK greater than 1MHz, pin 6 should be biased at 2V. This minimizes passband gain and phase variations.
ANALOG GROUND PLANE
1 2 3 4 5 6
7.5V 0.1F
7 8 9 10 11 12
STAR SYSTEM GROUND
* OPTIONAL, 1N4148, 1N5819
Figure 1. Dual Supply Ground Plane Connections
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24 23 22 -7.5V 21 20 19 LTC1264 18 17 16 15 14 13
ANALOG GROUND PLANE
1 2 3
24 23 22 21 20* 19 LTC1264 18 17* 16 15 14 13
*
0.1F
4 V
+
5k
*5
V +/2 6
+
1F 5k
V+
7
*8
9 10 11 12
DIGITAL GROUND PLANE
200 CLOCK SOURCE
1264 F01
STAR SYSTEM GROUND
DIGITAL GROUND PLANE
200 CLOCK SOURCE
* FOR MODE 3, THE S NODE PINS 5, 8,
17, 20 SHOULD BE TIED TO PIN 6
1264 F02
Figure 2. Single Supply Ground Plane Connections
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LTC1264
PI FU CTIO S
CLK (Pin 18): Clock Input Pin. Any TTL or CMOS clock source with a square wave output and 50% duty cycle (10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter's power supply. The analog ground for the filter should be connected to clock's ground at a single point only. Table 1 shows the clock's low and high level threshold values for a dual or single supply operation.
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY Dual Supply = 7.5V Dual Supply = 5V Dual Supply = 2.5V Single Supply = 12V Single Supply = 5V HIGH LEVEL 2.18V 1.45V 0.73V 7.80V 1.45V LOW LEVEL 0.5V 0.5V - 2.0V 6.5V 0.5V
A pulse generator can be used as a clock source provided the high level on-time is greater than 0.2s. Sine waves are not recommended for clock input frequencies less than 100kHz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time 1s). The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal path. A 200 resistor between clock source and Pin 11 will slow down the rise and fall times of the clock to further reduce charge coupling (Figures 1 and 2).
ODES OF OPERATIO
For the definition of filter functions please refer to the LTC1060 data sheet. Mode 1 In Mode 1, the ratio of the external clock frequency to the center frequency of each 2nd order section is internally fixed at 20:1. Figure 4 illustrates Mode 1 providing 2nd order notch, lowpass, and bandpass outputs. Mode 1 can be used to make high order Butterworth lowpass filters; it can also be used to make low Q notches and for cascading 2nd order bandpass functions tuned at the same center frequency. Mode 1 is faster than Mode 3.
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HPB/NB, BPB, LPB, LPA, BPA, HPA, HPD, BPD, LPD, LPC, BPC, HPC/NC (Pins 2, 3, 4, 9, 10, 11, 14, 15, 16, 21, 22, 23): Output Pins. Each 2nd order section of the LTC1264 has three outputs which typically source 3mA and sink 1mA. Driving coaxial cables or resistive loads less than 20k will degrade the total harmonic distortion performance of any filter design. When evaluating the distortion or noise performance of a particular filter design implemented with an LTC1264, the final output of the filter should be buffered with a wideband noninverting high slew rate amplifier (Figure 3).
-
5k LT1224
+
1264 F03
Figure 3. Wideband Buffer
INV B, INV A, INV D, INV C (Pins 1, 12, 13, 24): Inverting Input Pins. These pins are the high impedance inverting inputs of internal op amps and they are susceptible to stray capacitive connections to low impedance signal outputs and power supply lines. SB, SA, SD, SC (Pins 5, 8, 17, 20): Summing Input Pins. The summing pins connections determine the circuit topology (mode) of each 2nd order section. Please refer to Modes of Operation.
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Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC. Mode 1b Mode 1b is derived from Mode 1. In Mode 1b (Figure 5) two additional resistors R5 and R6 are added to alternate the amount of voltage fed back from the lowpass output into the input of the SA (SB, SC or SD) switched-capacitor summer. This allows the filter's clock-to-center frequency ratio to be adjusted beyond 20:1. Mode 1b maintains the speed advantages of Mode 1 and should be considered an
LTC1264
ODES OF OPERATIO
optimum mode for high Q designs with fCLK to fCUTOFF (or fCENTER) ratios greater than 20:1. Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC.
CC R3 R2 N VIN R1 S BP LP
- +
+
-
1/4 LTC1264 AGND f fi = CLK ; fO = fi; fn = fO 20 R3 R3 ; H = - R2 ; H Q= =- R1 OBP R1 R2 ON HOLP = HON
Figure 4. Mode 1, 2nd Order Filter Providing Notch, Bandpass and Lowpass Outputs
CC
R6 R3 R2 N VIN R1 S
R5
- +
AGND
+
-
1/4 LTC1264 NOTE: R5 5k
f R6 fi = CLK ; fO = fi ;f =f 20 (R6 + R5) n O R3 R6 ; H = - R2 ; H Q = R3 =- R1 OBP R1 R2 (R6 + R5) ON R2 R6 + R5 HOLP = - R6 R1
(
)
Figure 5. Mode 1b, 2nd Order Filter Providing Notch, Bandpass and Lowpass Outputs
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Mode 3 In Mode 3, the ratio of the external clock frequency to the center frequency of each 2nd order section can be adjusted above or below 20:1. Figure 6 illustrates Mode 3, the classical state variable configuration, providing highpass, bandpass, and lowpass 2nd order filter functions. Mode 3 is slower than Mode 1. Mode 3 can be used to make high order all-pole bandpass, lowpass, and highpass filters. Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC. Mode 2 Mode 2 is a combination of Mode 1 and Mode 3, shown in Figure 7. With Mode 2, the clock-to-center frequency ratio, fCLK /fO, is always less than 20:1. The advantage of Mode 2 is that it provides less sensitivity to resistor tolerances than does Mode 3. As in Mode 1, Mode 2 has a notch output which depends on the clock frequency, and the notch frequency is therefore less than the center frequency, fO. Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC.
CC
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R4
BP
LP
R3
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R2 HP VIN R1 S BP LP
- +
+
-
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1/4 LTC1264
AGND
f fi = CLK ; fO = fi 20
1 R3 R2 R2 R3 R4 ; Q = 1.005 (R2) R4 (1 - 6.42*R4)
R3 HOHP = - R2 ; HOBP = - R1 R1
(
1-
1 R3 6.42*R4
)
; HOLP = -
R4 R1
Figure 6. Mode 3, 2nd Order Section Providing Highpass, Bandpass and Lowpass Outputs
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LTC1264
ODES OF OPERATIO
CC R4 R3 R2 N S
VIN
R1
- +
+
-
1/4 LTC1264
AGND f fi = CLK ; fO = fi 20 R3 Q = 1.005 R2
( ) 1 + R2 1 - 1R3 R4 ( 6.42*R4 ) (1 + R2 ) R4
1 (DC GAIN, f < fn)
1 + R4 ; f = f
R2
n
O
HOHP = -
R2 (AC GAIN, f > fn); HOHPn = - R2 R1 R1 R3 R1
HOBP = -
(
1-
1 R3 6.42*R4
)
; HOLP = HOHPn
Figure 7. Mode 2, 2nd Order Filter Providing Highpass Notch, Bandpass and Lowpass Outputs
Mode 3a This is an extension of Mode 3 where the highpass and lowpass output are summed through two external resisCC R4 R3 R2 HP VIN R1 S BP
- +
1/4 LTC1264 AGND
Figure 8. Mode 3a, 2nd Order Filter Providing a Highpass Notch or Lowpass Notch Output
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BP LP
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tors RH and RL to create a notch. This is shown in Figure 8. Mode 3a is more versatile than Mode 2 because the notch frequency can be higher or lower than the center frequency of the 2nd order section. The external op amp of Figure 8 is not always required. When cascading the sections of the LTC1264, the highpass and lowpass outputs can be summed directly into the inverting input of the next section. Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC. Mode 2n This mode extends the circuit topology of Mode 3a to Mode 2 (Figure 9) where the highpass notch and lowpass outputs are summed through two external resistors RH and RL to create a lowpass output with a notch higher in frequency than the notch in Mode 2. This mode, shown in Figure 8, is most useful in lowpass elliptic designs. When cascading the sections of the LTC1264, the highpass notch and lowpass outputs can be summed directly into the inverting input of the next section. Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC.
LP
+
-
RH
RL
RG
R R f = f R4 1 R2 Q = 1.005 (R3) R2 R4 R3 1- ( 6.42*R4 ) R R (f = ) = ( ) ( R2 ) ; H (f = 0) = ( ) ( R4 ) H R R1 R R1 f fi = CLK ; fn = fi 20
H ;O L
R2
i
OHPn
G H
OLPn
G L
- +
HIGHPASS OR LOWPASS NOTCH OUTPUT EXTERNAL OP AMP OR INPUT OP AMP OF THE LTC1264, SIDES A, B, C, D
1264 G08
LTC1264
ODES OF OPERATIO
R4 R3 R2 HP VIN R1 S BP LP
- +
AGND
Figure 9. Mode 2n, 2nd Order Filter Providing a Lowpass Notch Output
BLOCK DIAGRA
INV A 12
- +
HPB/NB 2
AGND 6
INV B 1
- +
HPC/NC 23
INV C 24
- +
INV D 13
- +
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CC f fi = CLK ; fn = fi 1 + RH 20 RL R2 fO = fi 1+ R4 R R HOLPn (f = 0)= G + G R2 RH RL R1
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(
+
-
RH
RL
RG
Q = 1.005
R3 (R2) 1 + R2 R4
)( ) (
(
1-
1 1 + R2 R4
) )
1 R3 6.42*R4
- +
LOWPASS NOTCH OUTPUT EXTERNAL OP AMP OR INPUT OP AMP OF THE LTC1264, SIDES A, B, C, D
1/4 LTC1264
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HPA/NA 11
BPA 10
LPA 9 7 18 19 V+ CLK V-
+
-
8 SA
+
+
BPB 3
LPB 4
+
-
5 SB
+
+
BPC 22
LPC 21
+
-
20 SC
+
+
HPD/ND 14
BPD 15
LPD 16
+
-
17 SD
+
+
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LTC1264
APPLICATI
S I FOR ATIO
Operating Limits The Typical Maximum Q vs Clock Frequency and Bandpass Gain Error graphs, under Typical Performance Characteristics, define an upper limit of operating Q for each LTC1264 2nd order section. These graphs indicate the power supply, fCLK and Q value conditions under which a filter implemented with an LTC1264 will remain stable when operated at temperatures of 85C or less. For a 2nd order section, a bandpass gain error of 3dB or less is arbitrarily defined as a condition for stability. When the passband gain error begins to exceed 1dB, the use of capacitor CC will reduce the gain error (capacitor CC is connected from the lowpass node to the inverting node of a 2nd order section). Please refer to Figures 4 through 9. The value of CC can be best determined experimentally, and as a guide it should be about 5pF for each 1dB of gain error and not to exceed 15pF. When operating LTC1264 very near the limits defined by the Typical Performance Characteristics graphs, passband gain variations of 2dB or more should be expected. Speed Limitations To avoid op amp slew rate limiting, the signal amplitude should be kept below a specified level as shown in Table 2.
Table 2. Maximum VIN vs VS and Clock
VS 7.5V 5V Single 5V MAXIMUM CLOCK 4MHz to 5MHz 3MHz to 4MHz 1MHz to 2MHz MAXIMUM VIN 0.5VRMS fIN 400kHz 0.5VRMS fIN 250kHz 0.35VRMS fIN 160kHz
Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output pins. The clock feedthrough is tested with the filter's input grounded and it depends on PC board layout and on the value of the power supplies. With proper layout techniques, the typical values of clock feedthrough are listed under Electrical Characteristics. Any parasitic switching transients during the rise and fall edges of the incoming clock are not part of the clock Aliasing Aliasing is an inherent phenomenon of switched-capacitor filters and it occurs when the frequency of input signals approaches the sampling frequency. The input signals that produce the strongest aliased components have a frequency, fIN, such as (fSAMPLING - fIN) falls into the filter's passband. For the LTC1264 the sampling frequency is twice fCLK. If the input signal spectrum is not band-limited, aliasing may occur.
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feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The clock feedthrough, if bothersome, can be greatly reduced by adding a simple RC lowpass network at the final filter output. This RC will completely eliminate any switching transients. Wideband Noise The wideband noise of the filter is the total RMS value of the device's noise spectral density and it is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and it cannot be reduced with post filtering. The total wideband noise (VRMS) is nearly independent of the value of the clock. The clock feedthrough specifications are not part of the wideband noise. For a specific filter design, the total noise depends on the Q of each section and the cascade sequence. Table 3 shows typical 2nd order section noise (gain = 1) for Q values and supplies operating at 25C. Noise increases by 20% at the highest operating temperatures.
Table 3. 2nd Order Section Noise (VRMS) for Modes 1, 1b, 2 or 3 (R2 = R4)
Q 1 2 3 4 5 VS = 2.5V 40VRMS 50VRMS 60VRMS 75VRMS 90VRMS VS = 5V 50 60 75 90 110 VS = 7.5V 60 75 95 115 135
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LTC1264
APPLICATI S I FOR ATIO
For example, for an LTC1264 bandpass filter with fCENTER = 100kHz and fCLK = 2MHz, a 3.9MHz, 10mV input will produce a 100kHz, 10mV output. A 1st or 2nd order prefilter will reduce aliasing to acceptable levels in most cases. A GUIDE TO BANDPASS DESIGN Filter design tools like FCAD require design specification inputs such as passband ripple, attenuation, passband width and stopband width in order to calculate filter parameters fO, Q, fn or poles and zeroes. The results of these filter approximations most often require Q values which make excessive demands on the gain-bandwidth products of active filter realizations. The active filter designer should define a gain response so that the filter's mathematical approximation has practical requirements. Table 4 is a guide to practical design specifications for realizing bandpass filters with LTC1264 (please also refer to the Typical Maximum Q vs Clock Frequency and Bandpass Gain Error graphs under Typical Performance Characteristics). A Bandpass Design Example Filter Type: Filter Response: Passband Ripple: Attenuation: Center Frequency: Passband Width: Stopband Width: Bandpass Butterworth 3dB 60dB 40kHz (fCENTER) 10kHz 60kHz
R2 = 10k R5 = 5k f fi = CLK 20 R1 = R3 (FOR BANDPASS) HOBP R6 =
Implementing the Bandpass Design
R3 =
With the LTC1264 in Mode 1b, Butterworth and Chebyshev bandpass designs with fCLK to fCENTER ratios greater than 20:1 are possible. First choose the clock frequency which in Mode 1b must be greater than 20 times the bandpass center frequency of 40kHz. For this example, let's choose fCLK to be 1MHz. Table 6 lists the resistors for for the bandpass design example and Figure 11 shows the complete circuit.
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Table 4. Bandpass Design Specifications (fCENTER is center frequency of passband.)
PASSBAND RIPPLE (dB) 3dB for Butterworth 0.1 for Chebyshev PASSBAND WIDTH (Hz) fCENTER /20 fCENTER /20 STOPBAND ATTENUWIDTH ATION (Hz) (dB) 5 x Passband -40 to -60 5 x Passband -40 to -60 Note: Reducing passband ripple or attenuation will decrease Q values. The filter order may also increase.
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Table 5. Calculated Filter Parameters
STAGE 1 2 3 4 fO 38.1201kHz 41.9726kHz 35.6418kHz 44.8911kHz Q 4.3346 4.3346 10.5221 10.5221
Table 6. Calculated Mode 1b Resistors to Nearest 1% Value Using Table 5 Filter Parameters and Figure 10 Equations
STAGE 1 2 3 4 R1 52.3k 47.5k 56.2k 44.2k R2 10k 10k 10k 10k R3 56.2k 51.1k 147k 118k R5 5k 5k 5k 5k R6 6.98k 11.8k 5.11k 20.5k
( fi
R5*fO
2
2 2
- fO
2
)
fO
HOBP =
Q
(
fCENTER
)(
-
fCENTER fO
)
2
+1
R2*Q
(
R6 R6 + 5
)
1264 F10
Figure 10. Equations for Resistors in Mode 1b Operation
11
LTC1264
APPLICATI
R1 IN R2 R3
S I FOR ATIO
R1 INV C R2 HPC/NC R3 BPC LPC R5 LTC1264 SC V- CLK SD LPD R3 R2 fCLK R6 R6 R5
INV B HPB/NB
STAGE 1
BPB LPB R5 R6 R6 R5 SB AGND V+ SA LPA
R3 R2
HPA/NA INV A R1 R1
HPD/ND INV D OUT
GAIN (dB)
STAGE 3
BPA
BPD
Figure 11. Mode 1b Bandpass Filter
Figures 12 and 13 show the gain response graphs of the 40kHz Butterworth bandpass design described above. The passband gain response graph (Figure 12) shows a 40kHz gain of - 0.4dB and a tilted passband from 37kHz to 43kHz. These errors are due to the 1% resistors used and the sideto-side matching of the LTC1264 fCLK-to-fCENTER ratio which typically is 0.4%. To adjust for 0dB gain at 40kHz, reduce the value of R1 in the first stage by 5%. To adjust for a flat passband, adjust by 1% the value of R6 in stages 3 and 4. Adjusting R6 compensates for the side-to-side matching errors. Please refer to Figure 5 equations defining fO and Q as a function of R6. The sequence of 2nd order stages and the bandpass gain HOBP of each stage will determine the gain peaks at the filter's intermediate outputs. A given internal output can have several dB more gain than the final filter output. Gain peaks occur around the corners of the passband. The gain peaks can be reduced by increasing the R1 resistor of the
GAIN (dB)
12
U
STAGE 2
W
U
UO
first stage and decreasing the R1 resistor of the last stage by the same amount (multiplying the R1 resistor of the first stage and dividing the R1 resistor of the last stage by 2 for narrowband filter, and by 5 for wideband filter is a good rule of thumb). This adjustment may, however, increase the filter's passband noise.
1.0 0.5 0 -0.5 MODE 1b VS = 7.5V fCLK = 1MHz fCLK /fCENTER = 25:1
STAGE 4
-1.0 -1.5 -2.0 -2.5 -3.0
1264 F11
-3.5 -4.0 30 32 34 36 38 40 42 44 46 48 50 FREQUENCY (kHz)
1264 F12
Figure 12. Passband Gain vs Frequency 40kHz Butterworth Bandpass
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 10 18 26 34 42 50 58 66 74 82 90 FREQUENCY (kHz)
1264 F13
MODE 1b VS = 7.5V fCLK = 1MHz fCLK /fCENTER = 25:1
Figure 13. Gain vs Frequency 40kHz Butterworth Bandpass
LTC1264
TYPICAL APPLICATI
R1 IN 1 R2 HPB/NB R3 BPB R4 LPB C 0.1F 8V C R4 LPA R3 BPA R2 HPA/NA R1 IN 2 INV A R1 f -3dB (VS = 8V) 125kHz 200kHz 275kHz 400kHz
1264 TA04a
Linear Phase Clock-Tunable to 400kHz, Dual 4th Order Lowpass Filter
R1
0
INV B
LPC C LTC1264 SC V- CLK SD LPD R4 BPD R3 HPD/ND R2 INV D OUT 2 fCLK C 0.1F -8V
GAIN (dB)
SB AGND V+ SA
LTC1264 SIDE MODE R1 R2 R3 R4 C
B C 2 2 17.8k 20k 27.4k 27.4k 19.6k 21k 51.1k 75k 5pF 5pF
A 2 17.8k 27.4k 19.6k 51.1k 5pF
Clock-Tunable, fCENTER = fCLK /20, 100kHz, 4th Order Bandpass and Notch Filters
R1
10
R1 BANDPASS IN R2 HPB/NB R3 BPB LPB 0.1F SB AGND 7.5V V+ SA LPA R3 BPA R2 R1 NOTCH IN HPA/NA C INV A R1 LTC1264 SIDE MODE R1 R2 R3 C B 1 20k 10k 20k C 1 20k 10k 20k A 1 10k 10k 20k 10pF D 1 10k 10k 20k 10pF HPD/ND INV D C BPD R2 LTC1264 BPC LPC SC V- CLK SD LPD R3 NOTCH OUT fCLK 2MHz 0.1F - 7.5V HPC/NC R3 INV B INV C R2
GAIN (dB)
UO
S
Gain vs Frequency
OUT 1 INV C R2 HPC/NC R3 BPC R4
-10 -20 -30 -40 -50 -60 -70 -80 10k 100k FREQUENCY (Hz) 1M
1264 TA04b
D 2 20k 27.4k 21k 75k 5pF
fCLK 2MHz 3MHz 4MHz 5MHz
TA 50C
Gain vs Frequency
0 -10 -20
BANDPASS OUT
-30 -40 -50 -60 -70 VS = 7.5V fCLK = 2MHz 100k FREQUENCY (Hz) 1M
1264 TA05b
-80 10k
1264 TA05a
13
LTC1264
TYPICAL APPLICATI
R1
100kHz, 8th Order Notch Filter, fCLK /fCENTER = 20:1
10
R1 IN R2 HPB/NB R3 BPB LPB 0.1F SB AGND 7.5V V+ SA LPA R3 BPA R2 HPA/NA INV A R1 R1 HPD/ND INV D BPD R2 LTC1264 BPC LPC SC V- CLK SD LPD R3 fCLK 2MHz HPC/NC INV B INV C R2 R3
GAIN (dB)
Clock-Tunable, 8th Order Elliptic Lowpass Filter, fCLK /fCUTOFF = 20:1
RL RH R1 IN R2 HPB/NB R3 BPB R4 LPB 0.1F SB AGND 7.5V C R4 LPA R3 BPA R2 HPA/NA INV A RH RL HPD/ND R2 INV D OUT LTC1264 SIDE MODE R1 R2 R3 R4 RH RL C B C 3a 2n 27.4k 23.7k 20k 20k 37.4k 28k 100k 137k 100k 27.4k 31.6k 3pF A 2n 20k 37.4k 100k 130k 24.3k 3pF D 3 29.4k 19.1k 48.7k BPD R3 LPD R4 V+ SA LTC1264 LPC C SC V- CLK SD 0.1F RL fCLK 2MHz RH -80 10k -7.5V BPC R4 HPC/NC INV B INV C R2 R3 -10 -20 0
GAIN (dB)
1264 TA03a
14
UO
S
Gain vs Frequency
C
0 -10 -20 -30 -40 -50
-7.5V 0.1F
-60 -70 -80 10k VS = 7.5V fCLK = 2MHz 100k FREQUENCY (Hz) 1M
1264 TA06b
OUT
C
LTC1264 SIDE MODE R1 R2 R3 C
B C 1 1 36.5k 3.92k 10k 10k 50k 27.4k 30pF
A 1 7.5k 10k 50k
D 1 9.09k 10k 50k 30pF
1264 TA06a
Gain vs Frequency
VS = 7.5V fCLK = 2MHz
-30 -40 -50 -60 -70 100k FREQUENCY (Hz) 1M
1264 TA03b
POWER SUPPLY 7.5V 5V SINGLE 5V
MAXIMUM fCLK 3.6MHz (C = 10pF) 2.0MHz (C = 10pF) 1.6MHz (C = 10pF)
LTC1264
PACKAGE DESCRIPTIO
0.300 - 0.325 (7.620 - 8.255)
0.015 (0.381) MIN 0.009 - 0.015 (0.229 - 0.381)
0.005 (0.127) MIN +0.635 8.255 0.100 0.010 -0.381 (2.540 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
(
+0.025 0.325 -0.015
)
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0 - 8 TYP
0.009 - 0.013 (0.229 - 0.330)
NOTE 1
0.016 - 0.050 (0.406 - 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted. N Package 24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.265* (32.131) 24 23 22 21 20 19 18 17 16 15 14 13
0.255 0.015* (6.477 0.381)
1 0.130 0.005 (3.302 0.127)
2
3
4
5
6
7
8
9
10
11
12
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.018 0.003 (0.457 0.076)
N24 0695
0.125 (3.175) MIN
SW Package 24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.598 - 0.614* (15.190 - 15.600) 24 23 22 21 20 19 18 17 16 15 14 13
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
1 0.093 - 0.104 (2.362 - 2.642)
2
3
4
5
6
7
8
9
10
11
12 0.037 - 0.045 (0.940 - 1.143)
0.050 (1.270) TYP
0.004 - 0.012 (0.102 - 0.305)
0.014 - 0.019 (0.356 - 0.482)
S24 (WIDE) 0396
15
LTC1264
TYPICAL APPLICATI
R1 VIN INV B R2 HPB/NB R3 BPB R4 LPB 0.1F SB AGND 7.5V R4 LPA R3 BPA R2 HPA/NA INV A R1 RH HPD/ND INV D VOUT BPD R2 LPD R3 V+ SA LTC1264 LPC C SC V- CLK SD R4 1MHz -7.5V 0.1F BPC R4 HPC/NC R3 INV C R2 LTC1264 SIDE MODE R1 R2 R3 R4 RH RL fCLK 1MHz 1.5MHz 2.0MHz B C 3a 3 97.6k 10.7k 12.4k 39.2k 39.2k 13.3k 10.7k 53.6 15.0k A 3a 32.4k 10.7k 12.4k 11.5k D 3 10.0k 29.4k 10.0k 27.4k 100.0k
50kHz Bandpass Filter, Linear Phase Gain vs Frequency
10 0 -10 -20 VS = 7.5V fCLK = 1MHz
GAIN (dB)
GAIN (dB)
-30 -40 -50 -60 -70 -80 -90 10k 100k FREQUENCY (Hz) 1M
1264 TA07b
RELATED PARTS
PART NUMBER LTC1068 LTC1068-25 LTC1068-50 LTC1562 DESCRIPTION Very Low Noise, High Accuracy, Quad Universal Filter Building Block High Speed, High Accuracy, Quad Universal Filter Building Block Low Power, High Accuracy, Quad Universal Filter Building Block Very Low Noise, Low Distortion, Active RC Quad Universal Filter COMMENTS Four 2nd Order Filter Sections in 28-Pin SSOP, 56kHz Max Center Frequency, 40VRMS Noise per 2nd Order Section, Operation 3.3V to 5V Four 2nd Order Filter Sections in 28-Pin SSOP, 200kHz Max Center Frequency, Operation 3.3V to 5V Four 2nd Order Filter Sections in 28-Pin SSOP, 40kHz Max Center Frequency, 3.5mA at Single 5V, Operation 3.3V to 5V Four 2nd Order Filter Sections, No Clock Required, 150kHz Max Center Frequency, SSOP
1264fa LT/TP 0198 4K REV A * PRINTED IN USA
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
q
UO
8th Order Bandpass Filter, Linear Phase
RH RL C 0pF 5pF 10pF
1264 TA07a
RL
Passband Gain and Group Delay
3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 40 42 44 46 48 50 52 54 56 58 60 FREQUENCY (kHz)
1264 TA07c
124 GAIN 114 104 94 DELAY 84 74 64 54 44 34 24
GROUP DELAY (s)
(c) LINEAR TECHNOLOGY CORPORATION 1993

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